Integrated circuit chips are mounted in a lead frame which connects to the circuit board by two rows of bottom pins. A tiny bonding wire extends from each output pad on the chip to an adjacent pad on the lead frame, and a lead frame wire extends from the adjacent pad to one of the bottom pins. These two packaging wires combined could be as long as 2.5 cm, and with a distributed inductance of over 15 nanohenries.
As the output transistors are switched on and off, di/dt transients are generated in the output current flowing through the packaging wires connecting the pad to the circuit board. A typical "di" in the output current to a 32 channel load on the circuit board might be 4 milliamperes per channel or 128 milliamperes. A typical on-off switching time for an output transistor is about 2 nanoseconds.
The magnitude of the voltage spike generated along the packaging wires between the chip power pad and the bottom pin would be about: ##EQU1## The minimum voltage required to effect a change of state on the input of a 5 volt MOS device is on the order of 0.8 volts. These voltage spikes are generated on the power rails by the output transistors as they are switching; and cause troublesome random events in the chip circuitry. The massive distributed inductance of the conducting leads on the circuit board do not contribute to the inductive spike because of the grounding plane layer buried within the circuit board.
U.S. Pat. No. 4,723,108 to Colin N. Murphy and Robert G. Pugh teaches using a constant current source in the high-to-low side of the pull-down inverter for reducing the slew rate of the pull-down transistor. The slew rate is regulated by a reference voltage to the gate of the constant current source. Extending the switching time "dt" by slowing the slew rate reduces the output di/dt resulting in a lower voltage spike into the Vss rail.
U.S. patent application Ser. No. 246,634, filed Sept. 19, 1988 by Paul E. Platt and assigned to the present assignee, teaches a pair of pull-down current sources, one on each side of the pull-down inverter for controlling both the high-to-low slew rate and the low-to-high slew rate. Twin reference voltages for the two current sources are provided by a current mirror circuit. In one embodiment Platt discloses both the pull-down inverter and the pull-up inverter regulated by a single pair of current sources.